个人简介

刘双龙，男，1988年8月出生，博士、博士生导师、“潇湘学者”特聘教授、湖南省海外高层次人才计划获得者。2010年7月毕业于清华大学微纳电子系获得学士学位，2013年7月毕业于清华大学微电子所获得硕士学位，2017年9月获得英国帝国理工学院电子工程专业博士学位。2017年4月至2020年9月在帝国理工学院计算机系从事博士后研究工作（导师：Wayne Luk院士）。主要从事人工智能硬件加速器、计算机体系结构与并行计算系统研究。研究领域包括面向边缘计算的人工智能算法加速、粒子滤波硬件加速、贝叶斯算法加速和超光谱图像分割等。 迄今已在IEEE TNNLS、TCAD、TC、ACM TRETS、IEEE TAI等国际权威期刊及 DAC、FPGA、FCCM、DATE、ISCAS、FPL等CCF 推荐会议发表论文52 篇。已授权国家发明专利8项，公开国家及国际发明专利10项。主持国家自然科学基金项目、湖南省教育厅重点项目和湖南省自然科学基金项目等项目10余项。主持湖南省普通高等学校教学改革研究重点项目和湖南省教育厅研究生教改项目。获得湖南省高等教育教学成果奖二等奖、长沙市“星城杯”青年科技人才创新创业大赛二等奖、欧盟 HiPEAC 最佳论文奖及多项国际会议最佳论文提名。现任湖南省信息技术标准化技术委员会专家、湖南省企业科技特派员，国际会议ICSIP技术委员会委员等。

办公室：格物楼421

Ｅmail: liu.shuanglong@hunnu.edu.cn

学术贡献

1. Transformer等大模型算法压缩与硬件加速研究

针对视觉Transformer模型参数规模大、计算复杂度高、边缘设备部署困难等问题，设计高效的模型压缩策略，降低模型参数量和计算复杂度；结合硬件感知优化和加速器设计，实现视觉Transformer的高效推理。

2. 基于FPGA的高性能卷积神经网络加速器

主要研究人工智能中的深度卷积神经网络在边缘器件上的加速方法，包括高计算效率的硬件架构设计、频域卷积神经网络加速方法、硬件加速器的软硬件协同优化等内容。

3. 基于贝叶斯重采样的粒子滤波加速器

主要研究粒子滤波（序贯蒙特卡洛方法）算法及其应用。重点包括粒子滤波中的重采样方法及其硬件实现、粒子滤波算法的并行计算架构设计、粒子滤波硬件加速器的工具设计等。

4. 贝叶斯算法和贝叶斯神经网络的硬件加速

主要研究面向大数据的贝叶斯算法如马尔科夫蒙特卡洛（Markov Chain Monte Carlo，MCMC）的硬件加速方法。主要内容有基于低数值精度下的MCMC加速算法与系统设计、贝叶斯神经网络在硬件上的加速方法研究等。

*Research Positions！ 欢迎想在高性能计算、人工智能硬件加速器和集成电路设计交叉领域从事相关研究的优秀青年加入课题组，攻读硕士、博士或博士后！提供经费和平台支持，并提供参加国际学术会议和国际交流的机会。

*要求：专业基础扎实、对科研感兴趣、勤奋刻苦。欢迎邮件联系。

教学情况

本科生教学：《电路分析》《数字电子技术》《电工学》

研究生教学：《嵌入式系统及应用》《计算机视觉》

承担课题

1. 国家自然科学基金项目，62001165, 基于贝叶斯重采样的粒子滤波算法及其硬件实现研究,，2021/01-2023/12，结题，主持

2. 湖南省教育厅重点项目, 23A0087, 基于FPGA的分布式粒子滤波加速器的设计和应用研究, 2024-01至 2026-12，在研，主持

3. 长沙市自然科学基金, kq2502001, 高效粒子交互的分布式粒子滤波方法与硬件加速, 2024-01 至 2026-12, 在研，主持

4. 湖南省自然科学基金青年基金项目, 2021JJ40357, 基于贝叶斯重采样的粒子滤波算法及其硬件加速, 2021-01 至 2023-12, 结题, 主持

5. 长沙市自然科学基金, kq2014079,随机重采样粒子滤波器的硬件加速与应用, 2021-01 至 2023-12, 结题，主持

6. 英国官方365上市“潇湘学者” 特聘教授启动经费，面向人工智能的高性能计算芯片和系统设计，2021/01-今，在研，主持

7. 英国官方365上市科技成果转化项目，面向边缘计算的高性能人工智能硬件加速器，2026/07-今，在研，主持

代表性学术论文

2026年

1.S Liu*, Y Zhou, H Yuan, R He, J Jiang, FPGA-Accelerated Fully Spectral CNNs for Real-Time Semantic Segmentation, 2026 IEEE International Symposium on Circuits and Systems (ISCAS)，2026 (CCF-B).

2.S Liu*, X Wang, B Zhou, W Luo, J Liu, J Ma, Adaptive-Fusion Particle Filter with Distributed Resampling and Dynamic Particle Scaling, 2026 IEEE International Symposium on Circuits and Systems (ISCAS)，2026 (CCF-B).

3. W Shen, H Yuan,S Liu*，CMP-LSTM: Accuracy-Driven Column-Wise Maximum Pruning for Efficient LSTM Acceleration，IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD)，2026 (CCF-A).

2025年

5. Y Gong, X Wang, Y Zhou, J Ma,S Liu*,Distributed Particle Filter with Novel Hybrid Resampling and Balanced Workload, 2025 10th International Conference on Signal and Image Processing (ICSIP),2025.

6. J Jiang, Y Zhou, Y Gong, H Yuan,S Liu*, Fpga-based acceleration for convolutional neural networks: A comprehensive review, arXiv preprint arXiv:2505.13461, 2025.

7.S Liu*, S Peng, W Shen, FPGA-Based Acceleration of MCMC Algorithm through Self-Shrinking for Big Data, 2025 Design, Automation & Test in Europe Conference (DATE),2025 (CCF-B).

2024年

8. W Shen, J Jiang, M Li,S Liu*, Efficient CORDIC-based activation functions for RNN acceleration on FPGAs,IEEE Transactions on Artificial Intelligence, 2024.

9. K Dai, Z Xie,S Liu*, DCP-CNN: Efficient acceleration of CNNs with dynamic computing parallelism on FPGA, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)，2024 (CCF-A).

10. F Wang, S Peng, Y Gong, M Li,S Liu*, Algorithm and Hardware Co-Design for Efficient PMCMC Acceleration on FPGA, 2024 9th International Conference on Signal and Image Processing (ICSIP),2024.

11. Z Xie, K Dai, Z Wu, J Wang, X Lu,S Liu*, Design space exploration of cnn accelerators based on gsa algorithm, 2024 9th International Conference on Signal and Image Processing (ICSIP),2024.

12. HM Chen, L Castelli, M Ferianc, H Zhou,S Liu, W Luk, H Fan, Enhancing dropout-based Bayesian neural networks with multi-exit on FPGA, arXiv preprint arXiv:2406.14593, 2024.

2023年

13. M Xie, Z Wu, X Li,S Liu*, Design of ess-based adaptive particle filter for real-time tracking, 2023 8th International Conference on Signal and Image Processing (ICSIP),2023.

14. S Liu*, M Xie, HC Ng, H Guo, X Li, Improving particle filters with adaptive bayesian resampling for real-time filtering, 2023 8th International Conference on Signal and Image Processing (ICSIP),2023.

2022年

15.S Liu*, H Fan, W Luk, Design of fully spectral cnns for efficient fpga-based acceleration, IEEE Transactions on Neural Networks and Learning Systems (TNNLS),2022 (校定TOP).

16. H Fan, M Ferianc, Z Que,S Liu, X Niu, MRD Rodrigues, W Luk, FPGA-based acceleration for Bayesian convolutional neural networks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)，2022 (CCF-A).

17. H Fan, M Ferianc, Z Que, H Li,S Liu, X Niu, W Luk, Algorithm and hardware co-design for reconfigurable cnn accelerator, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022 (CCF-C).

2021年

18.S Liu*, H. Fan, M. Ferianc, X. Niu, H. Shi, W. Luk, Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs, IEEE Transactions on Neural Networks and Learning Systems (TNNLS),2021 (校定TOP).

19. H. Fan,S Liu*, Z. Que, X. Niu, W. Luk, High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point, IEEE Transactions on Neural Networks and Learning Systems (TNNLS),2021 (校定TOP).

20.S Liu*, H. Fan, and W. Luk, “Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA,” in Design, Automation and Test in Europe Conference (DATE), 2021 (CCF-B).

21. H.-C. Ng, I. Coleman,S. Liu, and W. Luk, Reconfigurable Acceleration of Short Read Mapping with Biological Consideration, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2021 (CCF-B).

2020年及以前

22.S Liu*,W Luk, Optimizing Fully Spectral Convolutional Neural Networks on FPGA, IEEE International Conference on Field Programmable Technology (FPT), 2020 (CCF-C).

23. H.-C. Ng,S. Liu,I. Coleman, W. Luk, Acceleration of Short Read Alignment: Exploration of Speed vs Accuracy with Different Strategies, IEEE International Conference on Field Programmable Technology (FPT), 2020 (CCF-C).

24. H. Fan, M. Ferianc,S. Liu, and W. Luk, “RNAS: Reconfigurable CNN Accelerator with Differentiable Neural Architecture Search,” in IEEE International Conference on Computer Design (ICCD), 2020.

25.S Liu*, and Wayne Luk. "Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs." In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019 (CCF-C).

26.S Liu*, Fan, H., Niu, X., Ng, H. C., Chu, Y., & Luk, W. Optimizing cnn-based segmentation with deeply customized convolutional and deconvolutional architectures on fpga. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 11(3), 1-22，2018.

27.S Liu*, R. Chu, X. Wang, and W. Luk, “Optimizing CNN-based Hyperspectral Image Classification on FPGAs," in 15th International Symposium on Applied Reconfigurable Computing (ARC), 2018.

28.S Liu*, C. Zeng, H. Fan, H.-C. Ng, J. Meng, and W. Luk, “Memory-Efficient Architecture for Accelerating Generative Networks on FPGAs," in IEEE International Conference on Field Programmable Technology (FPT), 2018.

29. H. Fan,S Liu*, M. Ferianc, and W. Luk, “A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA," in IEEE International Conference on Field Programmable Technology (FPT), 2018.

30.S Liu*, G. Mingas, and C.-S. Bouganis, “An unbiased mcmc fpga-based accelerator in the land of custom precision arithmetic,"IEEE Transactions on Computers, 2017 (CCF-A).

31. R. Zhao,S. Liu, H. Ng, E. Wang, J. Davis, X. Niu, X. Wang, H. Shi, G. Constantinides, P. Cheung, and W. Luk, “Hardware compilation of deep neural networks: An overview," in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018.

32.S Liu*, X. Niu, and W. Luk, “A low-power deconvolutional accelerator for convolutional neural network based segmentation on fpga," in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018.

33.S Liu* and C.-S. Bouganis, “Communication-aware mcmc method for big data applications on fpgas," in IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2017.

34.S Liu*, G. Mingas, and C.-S. Bouganis, “An exact mcmc accelerator under custom precision regimes," in IEEE International Conference on Field Programmable Technology (FPT), 2015.

35.S Liu*, G. Mingas, and C.-S. Bouganis, “Parallel resampling for particle filters on fpgas," in IEEE International Conference on Field-Programmable Technology (FPT), 2014.

授权专利

1.刘双龙; 龚源昊; 沈万; 周博通; 马嘉琦; 基于逐列最大化剪枝的LSTM硬件加速器, 2025-08-22, 中国, CN202510788755.0.

2.刘双龙;彭石玉；袁豪轩；龚源昊;一种基于自适应数据子采样的MCMC加速方法和加速器, 2025-10-10, 中国, CN202411916893.4.

3.刘双龙; 戴奎; 谢哲韧; 基于动态可重构并行计算的CNN硬件加速方法和加速器, 2026-02-03, 中国, CN202210947397.X.

4.刘双龙; 谢哲韧; 戴奎; 汪锦玥; 基于退火法的动态可重构卷积神经网络加速器及其参数优化方法,2025-10-17,中国, CN202310734188.1.

5.刘双龙；伍治林；谢明珠；李响; 随机排列生成器及基于其的分布式粒子滤波方法、加速器, 2025-09-26, CN202211621285.1.

6.刘双龙; 基于自适应ReLU的全频域卷积神经网络的硬件加速器、加速方法和图像分类方法, 2022-04-12, 中国, CN202011637130.8.

7.刘双龙; 全频域卷积神经网络的硬件加速器、加速方法和图像分类方法, 2022-04-08, 中国, CN202011640252.2.

8.刘双龙; 一种基于贝叶斯重采样的粒子滤波的FPGA硬件实现方法、装置及目标跟踪方法, 2022-03-25, 中国, CN202110085423.8.

获奖情况

1.湖南省海外高层次人才计划, 2020年度

2.长沙市“星城杯”青年科技人才创新创业大赛二等奖, 2021年度

3.湖南省高等教育（本科）教学成果奖一等奖, 2022年度

4.欧洲HiPEAC委员会最佳论文奖, 2017年度

5.Imperial College President's PhD Scholarships（2013年）